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The delay time depends on the variety of image parts included inside a block. The video sign is provided from the delay circuit 2a to a subtractor 2b. Here the difference between the image signal, and the prediction signal equipped through a line 105a branching from an output line 105 of a prediction sign generator 5, is produced, and the distinction, i.e. the prediction error sign, is then equipped to a quantizer three which features to restrict the variety of potential ranges.

The expanded and separated data representing the optimum prediction function and prediction error signal are supplied to a prediction sign generator 12 and an adder thirteen through lines and 211-1, respectively. The prediction sign generator 12 generates the optimum prediction sign in accordance with data representing the optimum prediction function, and the perform and structure of the generator are the same as these of the prediction sign generator 5 within the predictive coding system. The generated prediction sign is provided by way of line 212 to the adder thirteen and added to the prediction error signal supplied by way of line 211-1, in order that a video sign is reproduced. The reproduced video signal is then supplied to a scan inverter circuit 14 and a delay circuit 15 via an interpolator 16 and lines 213a and 213b branching from line 213. The interpolator 16 related to the code expander eleven by way of a line 216 matches the interpolator 302 as proven in FIG.

One great post to read of four parallel picture component outputs is equipped by way of line 108-6a to a subtractor 8-12a, proven in FIG. The place of an image element processed by the arithmetic unit 8-1 shall be known as hereinafter image factor level D1 as shown in FIG. 3A. Similarly, different arithmetic items 8-2 through 8-4 are used for computing image element points D2 via D4, and four arithmetic items in total are utilized in parallel for concurrent computations for one block. Line reminiscence pair 1-1 and 1-2 and another line memory pair 1-3 and 1-4 are stored and browse out alternately, so that the video signal which is rendered scan conversion i.e. converted into two-dimensional blocks, is output in a string of picture parts. One of two outputs from a line reminiscence pair in reading operation is selectively output through the multiplexor 1-5. The block-formation video signal on a line one hundred and one from the multiplexor 1-5 branches to the strains 101a and 101b, then is provided to the delay circuit 2a and optimum prediction detector check here eight, respectively. The above-mentioned scan conversion is advantageous because the predictive coding circuit using the two-dimensional blocks is straightforward.

9 is a block diagram displaying in detail the prediction signal generator 5 in FIG. 4A. In the figure, a two-dimensional reminiscence 5-1 has considerably the same construction as that of the two-dimensional memory 8-11 included in the arithmetic unit 8-1.

5 is a block diagram showing in detail the scan converter 1 of FIG. 4A. In this embodiment, 2×2 two-dimensional blocks every consisting of two image components in the horizontal path and two traces in the get redirected here vertical direction, as shown in FIG. One block includes four image elements, e.g. a11, a12, a21 and a22, enclosed by damaged line. In a basic tv system, the display is scanned from left to right in the order of, for example, a11, a12 , a13 and a14, and components a21, a22, a23 check my blog and a24 are included on the succeeding scanning line.

Consequently, the code size of the prediction perform representing the inter-frame prediction could be made roughly zero at the vector code size generator 8-14. The code length of a prediction perform of the prediction other than the inter-frame may optionally be determined but ideally, its size may be elevated because the diploma of departure from the inter-frame prediction increases.

For the predictive coding system using movement compensation, the range of correction, i.e., the number of vectors N, should ideally be as giant as possible and the variety of picture elements in a block be as small as attainable. From this viewpoint, the tactic of during which essential hardware is decided by the worth of N and a extensive range of movement compensation disadvantageously wants an elevated hardware. In contrast, the strategy of mainly uses M arithmetic items repeatedly for N instances, and the hardware requirement is just about determined by the value of M. Thus, it can be seen that the method of is more advantageous. The handle of the prediction signal generator memory 8-11a for writing the above-mentioned supplementary picture components is preferably subsequent to the addresses for storing picture components that are needed for figuring out the optimum prediction operate for the present block, for facilitating read/write control. For this objective, A1 through A8 are written following the addresses for storing x1 through x16 as shown in FIG. The necessary storage capability of the prediction signal generator memory 8-11a is expressed, using symbols k, L, m and n, as (2m+k)×(2n+L) for determining the optimum prediction operate of the current block, k×(2n+L) for supplementary image components for figuring out the optimum prediction operate of the following block, amounting to 2(m+k)×(2n+L) in total.